The present invention relates to an insulate gate transistor that has an insulated gate structure formed of a metal layer, an oxide layer and a semiconductor layer.
FIG. 10 is a cross sectional view of the unit structure (the so-called xe2x80x9chalf cellxe2x80x9d) of a conventional insulate gate bipolar transistor (hereinafter referred to as an xe2x80x9cIGBTxe2x80x9d), that is a type of insulate gate transistor. Referring now to FIG. 10, a p-type well region 4 is in the surface portion of an n-type drift layer 3. A heavily doped p+-type contact region 5 is in p-type well region 4. An n-type emitter region 6 is in the surface portions of p-type well region 4 and p+-type contact region 5. A gate electrode 7 is above the semiconductor structure with a gate oxide film 10 interposed therebetween from n-type emitter region 6 to n-type emitter regions 6 of the adjacent unit structure. An emitter electrode 9 is in common contact with n-type emitter region 6 and p+-type contact region 5. A collector layer 2 is on the back surface of n-type drift layer 3. A collector electrode 1 is on the back surface of collector layer 2. Emitter electrode 9 is extended above gate electrode 7 with an interlayer insulation film 8 interposed therebetween.
FIG. 11 shows cross sectional views explaining the steps 11(a) through 11(f) for manufacturing the IGBT of FIG. 10. In FIG. 11, only the emitter side of the IGBT is shown for the sake of simplicity. Referring now to the cross section (a) of FIG. 11, a thin gate oxide film 10 is formed on n-type drift layer 3 by thermal oxidation. A polycrystalline silicon film is deposited on gate oxide film 10, and a gate electrode 7 is formed by patterning the deposited polycrystalline silicon film by photolithography. As shown in FIG. 11(b), boron ions 14a are selectively implanted using gate electrode 7 as a mask. The implanted boron atoms are designated by a reference numeral 14b. Referring now to FIG. 11(c), a p-type well region 4 is formed by activating implanted boron atoms 14b by a heat treatment. Boron ions 15a are selectively implanted using a patterned photoresist 11 as a mask for the ion implantation as shown in FIG. 11(d). The implanted boron atoms are designated by a reference numeral 15b. Referring now to FIG. 11(e), arsenic ions 16a are implanted using gate electrode 7 and a patterned photoresist 12 as masks for the ion implantation. The implanted arsenic atoms are designated by a reference numeral 16b. As shown in FIG. 11(f), p+-type contact region 5 and n-type emitter region 6 are formed by activating the implanted boron atoms 15b and the implanted arsenic atoms 16b by a heat treatment. According to the manufacturing method described above, p-type well region 4 and n-type emitter region 6 are self-aligned by ion implantation using the same gate electrode 7 as a mask for defining one end of p-type well region 4 and one end of n-type emitter region 6.
In the IGBT exhibiting the breakdown voltage of the 600 V class, p-type well region 4 is 4 xcexcm in depth, p+-type contact region 5 is 3 xcexcm in depth, and n-type emitter region 6 is 0.3 xcexcm in depth. And, the width of the surface portion of p-type well region 4 between n-type emitter region 6 and n-type drift layer 3, that is the channel length, is about 1 xcexcm.
Recently, the diffusion depth of the p-type well region has become reduced to reduce the loss of the IGBT (cf. M. Otsuki, et. al., xe2x80x9cThe 3rd generation IGBT toward a limit of IGBT performancexe2x80x9d, Proc. ISPSD ""93, pp. 24-29, (1993), and T. Kushida, et. al., xe2x80x9cA He irradiated IGBT with a shallow p-base and shallow FLRsxe2x80x9d, Proc. ISPSD xe2x80x297, pp. 277-280, (1997)).
However, when the diffusion depth of the p-type well region is limited to be shallow, the lateral diffusion length is shortened, resulting in a shortened channel length. Due to the shortened channel length, the current caused by short-circuiting of the load (load short-circuit current) is increased and, therefore, the short circuit withstand capability of the device is reduced.
Various countermeasures have been proposed to obviate the above described problem and to secure a certain short circuit withstand capability. The proposed countermeasures include patterning the emitter structure for shortening the channel length in the MOS structure (cf. Akio Nakagawa, DE 3 519 389 A1) and combining n-type and n+-type impurity distributions for forming the emitter region (J. Zeng, et. al., xe2x80x9cDesign of IGBTs for Latch-up Free Operationxe2x80x9d, Solid State Electronics vol. 37, No. 8, pp. 1471-1475, (1994), and Kenji Suzuki, EP 0 336 393 A2).
The countermeasures described above, however, obtain a sufficient short circuit withstand capability at the sacrifice of on-state voltage drop of the device. Although the electrons injected into the n-type drift layer of the IGBT may be controlled, the above described countermeasures are not so effective to improve the latch-up withstand capability of the npn transistor formed of an n-type emitter region, a p-type well region and an n-type drift layer. Due to the unimproved latch-up withstand capability, it is impossible to prevent the parasitic npnp thyristor, formed of n-type emitter region 6, p-type well region 4, n-type drift layer 3 and p-type collector layer 2, from latching up.
In the ON-state of the IGBT, the injected electron current Id (in the saturation region) is expressed by the following equation.
Id=(Z/L)xcexcCo(Vgxe2x88x92Vth)2xe2x80x83xe2x80x83Eq. (1)
Here, Z is the circumferential length of the channel region, L the channel length, Co the gate capacitance, Vg the gate voltage and Vth the threshold value.
The IGBT is a device that uses the injected electron current as a base current to drive the pnp transistor formed of p-type well region 4, n-type drift layer 3 and p-type collector layer 2. The on-voltage of the IGBT has been reduced so far by increasing Z, by shortening L and by lowering Vth. The most popular way of reducing the on-voltage is to reduce the diffusion depth of the p-type well region so that the channel length L may be shortened.
FIG. 12 is a cross sectional view for analyzing the on-voltage components in the IGBT. Referring now to FIG. 12, the on-voltage of the IGBT consists of a voltage drop 20 across the channel resistance in a channel region 17 in the surface portion of p-type well region 4, a parasitic junction FET (JFET) component 21 formed of p-type well regions 4 and 4 on both sides and n-type drift layer 3, a voltage drop 22 in n-type drift layer 3, and a voltage drop 23 in p-type collector layer 2.
The reduction of the on-voltage by reducing the diffusion depth of p-type well region 4 is attributed to the reduction of the voltage drop 20 in channel region 17 and the reduction of the JFET component 21. Since the load short-circuit current is defined by the foregoing equation (1), the short circuit withstand capability in the short-circuiting of the load is reduced as the short-circuit current is larger.
It is important for the practical power device to exhibit a low on-voltage and a small short-circuit current. However, there exists a close relation between the on-voltage and the short circuit withstand capability. Shortening of the channel length by shallowly diffusing p-type well region 4 causes reduction of the short circuit withstand capability of the device, since the short diffusion depth of p-type well region 4, that lowers the on-voltage (reduces the loss), increases the short-circuit current.
Thus, it is substantially impossible for the foregoing countermeasures to independently control the channel length and the diffusion depth, i.e. the reduction of the on-voltage and the increase of the short-circuit current by shortening the channel length of the MOSFET and the reduction of the on-voltage by reducing the parasitic JFET component.
In view of the foregoing, it is an object of the invention to provide an IGBT that exhibits a low on-voltage and a sufficient short circuit withstand capability. It is another object of the invention to provide a method of manufacturing such an IGBT.
The invention providea an IGBT that exhibits a low on-voltage and a sufficient short circuit withstand capability and a method of manufacturing such an IGBT.
According to the invention, the well region of the second conductivity type and the emitter region of the first conductivity type are not formed by double diffusion using the gate electrode as a common mask. The well region and the emitter region are formed with a certain offset left beneath the gate electrode.
According to an aspect of the invention, there is provided an insulated gate transistor including: a lightly doped drift layer of a first conductivity type; a well region of a second conductivity type in the surface portion of the drift layer; an emitter region of the first conductivity type in the well region; a channel region in the extended portion of the well region extended between the emitter region and the drift layer; a gate electrode above the extended portion of the well region with a gate oxide film interposed therebetween; an emitter electrode in common contact with the well region and the emitter region; a collector electrode on the back surface of the drift layer; and an offset portion introduced into the extended portion of the well region to expand the width of the channel region.
The channel length is controlled by adjusting the width of the offset portion (offset length) and the diffusion depth is controlled independently of the channel length by adjusting the conditions for driving the channel region. The short-circuit current is reduced, that is, a certain short circuit withstand capability is secured, by expanding the channel length to some extent and the on-voltage is lowered by reducing the diffusion depth of the well region in the same insulated gate transistor.
According to another aspect of the invention, there is provided the method of manufacturing an insulated gate transistor, including a lightly doped drift layer of a first conductivity type, a well region of a second conductivity type in the surface portion of the drift layer, an emitter region of the first conductivity type in the well region, a channel region in the extended portion of the well region extended between the emitter region and the drift layer, a gate electrode above the extended portion of the well region with a gate oxide film interposed therebetween, an emitter electrode in common contact with the well region and the emitter region, and a collector electrode on the back surface of the drift layer, the method including: changing the effective mask edge location by an offset length between forming the well region and forming the emitter region to expand the width of the channel region.
The expanded width of the channel region, expanded by the offset length by the manufacturing method according to the invention, suppresses the JFET component of the on-voltage at a minimum value and secures a channel length long enough to obtain a certain short circuit withstand capability.
Preferably, the width of the offset portion (offset length) is from 0.5 to 5.0 xcexcm. When the offset length is shorter than 0.5 xcexcm, the short circuit withstand capability is small. When the offset length is longer than 5.0 xcexcm, the on-voltage is too high. Therefore, the offset length outside the range between 0.5 xcexcm and 5.0 xcexcm is not practical.
The impurity concentration beneath the surface of the extended portion of the well region is preferably constant for the width of 0.5 xcexcm or more.
According to the manufacturing method of the invention, the impurity concentration beneath the surface of the p-type well region is constant for the offset length. The region, therein the impurity concentration is constant, proves that the p-type well region and the n-type well region are offset from each other.
Preferably, different masks are used for implanting the impurity ions to form the p-type well region and to form the n-type emitter region. By using different masks, the p-type well region and the n-type well region are offset from each other easily. The masks, the thickness thereof is different, are used and the acceleration voltage is changed for implanting the impurity ions to form the p-type well region and to form the n-type emitter region.
Preferably, a common mask, the thickness thereof is tapered, is used for implanting the impurity ions to form the p-type well region and to form the n-type emitter region. The common mask is preferably made of polycrystalline silicon, the polycrystalline silicon mask is damaged by ion implantation, and the mask is provide with a tapered edge portion, formed by utilizing the etching rate difference between the polycrystalline silicon and the damaged layer. The polycrystalline silicon mask having a tapered edge portion facilitates offsetting the p-type well region and the n-type emitter region from each other.
According to still another aspect of the invention, there is provided a trench-type insulated gate transistor including: a lightly doped drift layer of a first conductivity type; a well region of a second conductivity type in the surface portion of the drift layer; an emitter region of the first conductivity type in the well region; a trench dug from the surface of the emitter region down to the drift layer; a channel region in the well region, the channel region facing to the trench, the thickness of the channel region being from 8 to 20 xcexcm; a gate electrode above the surface of the channel region with a gate oxide film interposed therebetween; an emitter electrode in common contact with the well region and the emitter region; and a collector electrode on the back surface of the drift layer.
When the thickness of the channel region (channel length) is shorter than 8 xcexcm, the short circuit withstand capability is small. When the channel length is longer than 20 xcexcm, the on-voltage is too high. Therefore, the channel length outside the range between 8 xcexcm and 20 xcexcm is not practical for the trench-type insulated gate transistor.
Other features and advantages of the invention will be come apparent to those of ordinary skill in the art from the following detailed description of the preferred embodiments of the invention and the accompanying drawings.